Hello, I'M Eric

Graduate Student @ UW-Madison





Ehsan (Eric) Qasemi

My name is Eric(Ehsan) Qasemi. I am a graduate student at University of Wisconsin Madison pursuing master's Degree in Computer Science, Computer Engineering, and a certificate in Entrepreneurship. I am honored to get my B.Sc in Elecetrical Engineering: Digital Systems from University of Tehran (UT). During my professional life, I have done projects in BigData, Bioinformatics, Machine Learning, Computer Security, high-performance computing, embedded systems, secure hardware, data analysis, and computer architecture. Feel free to check my GitHub and contact me if you have any feedback about my website or want to talk about my projects.

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RESUME CV LONG BIO

Education


MSC. IN COMPUTER SCIENCE(GPA 3.53/4): University of Wisconsin at Madison (2015-Present)

Notable Coursework: Machine Learning (CS760), Information Security(CS642), Theory & application of Pattern Recognition(CS532), HPC in Engineering(CS759), Optimization(CS524), Intro. Operating Systems(CS537), DataBase Managements Sys. (CS564), BigData (CS744), Data Visualization (CS765).

MSC. IN COMPUTER ENGINEERING (GPA 3.53/4): University of Wisconsin at Madison (2015-2017)

Notable Coursework:
Advnaced Computer Architecture (ECE/CS752), Computer-Aided Design for VLSI(ECE/CS756), Modern Probability Theory and Stochastic Processes(ECE730)

Certificate IN Entrepreneurship (GPA 3.50/4): University of Wisconsin at Madison (2015-2017)

Notable Coursework:
Strategic Management of Innovation (MHR715), Human Resource Managment(MHR705), Entrepreneurial Management(MHR722), Technology Entrepreneurship(MHR741)

BSC. IN ELECTRONICS ENGINEERING :DIGITAL SYSTEMS. (GPA 16.12/20): University of Tehran (2010-2015)

Notable Coursework:
Digital Signal Processing, Computer Network, Data Structure & Algorithm, Parallel Programming, OO Modeling, Verification


MY SKILL SET

C/C++
25% Complete (success)
Python
25% Complete (warning)
Java
25% Complete (danger)
Scala
25% Complete (danger)
Matlab
25% Complete (success)
Julia
25% Complete (warning)
R
25% Complete (danger)
Octave
25% Complete (danger)
Cuda
25% Complete (success)
OpenCl
25% Complete (warning)
Lua
25% Complete (danger)
Assembly (X86, Arm, Mips)
25% Complete (danger)
MPI
25% Complete (success)
OpenMP
25% Complete (warning)
SQL
25% Complete (danger)
Charm++
25% Complete (danger)
HTML
25% Complete (success)
CSS
25% Complete (warning)
JavaScript
25% Complete (danger)
VBA
25% Complete (danger)
Verilog/SystemVerilog
25% Complete (success)
VHDL
25% Complete (warning)
Chisel
25% Complete (danger)
SystemC/System C-Ams
25% Complete (danger)
Pandas
25% Complete (success)
Keras
25% Complete (warning)
RocksDB
25% Complete (danger)
SQL-Lite
25% Complete (danger)
Numpy
25% Complete (success)
SciPy
25% Complete (warning)
MatPlotLib
25% Complete (danger)
scikit-learn
25% Complete (danger)
PyQt
25% Complete (success)
JuMP
25% Complete (warning)
Cplex
25% Complete (danger)
Gorubi
25% Complete (danger)
Hadoop
25% Complete (success)
Spark
25% Complete (warning)
Hive
25% Complete (danger)
Tez
25% Complete (danger)
Linux
25% Complete (success)
Windows
25% Complete (warning)
Android
25% Complete (danger)
Gem5
25% Complete (danger)
Atmel MicroControllers
25% Complete (success)
Xillinx ISE/Vivado
25% Complete (warning)
Altera Quartus
25% Complete (danger)
Simulink
25% Complete (danger)

Research and Publications

Under Supervission of Prof. A. H. Assadi

Jul 2017-Present


Keywords:
Deep Learning Bigdata DataScience Spatiotemporal Data Image Processing

Highlights:
  • Big data local-to-global methods in analysis and prediction of dynamics in atmospheric chemistry spatiotemporal data.
  • Inverse problems in brain activation dynamics using multiple modalities (fMRI, EEG, and DTI)
Publications:
  1. ACCEPTED: Z. Liz Li, E. Qasemi, A. Ardalan, H. Gao, A. H. Assadi, “A Computational Model for Mental Face Spaces: Deep Learning Empirical Space of Faces”, The 2017 International Conference on Computational Science and Computational Intelligence (CSCI 17), Dec 2017, Las Vegas, USA
  2. ACCEPTED: A. H. Assadi, P. Han, E. Qasemi, A. Ardalan, H. Gao, “Deep Learning Empirical Topology for Classical Music Style Decision Making”, The 2017 International Conference on Computational Science and Computational Intelligence (CSCI 17), Dec 2017, Las Vegas, USA
  3. ACCEPTED: S. Yuchen, E. Qasemi, A. Ardalan, H. Gao, A. H. Assadi, “Deep Learning Art History from Data: Baroque Intellectual Influence on the Romantic Era Painting”, The 2017 International Conference on Computational Science and Computational Intelligence (CSCI 17), Dec 2017, Las Vegas, USA

Under Supervission of Prof. A. H. Assadi

Dec 2016-Present


Keywords:
Clustering Autism Entropy Method Deep Learning Bigdata DataScience Spatiotemporal Data Kinect

Highlights:
  • research and development in big data science methods: Manage and process massive heterogeneous spatiotemporal data sets and BIG DATA that includes time-series data, video, genome sequence etc.
  • Research team member for the project: novel clustering and data visualization methods for discovery of ASD personalized therapy.
  • propose an architecture based on Deep Recurrent Neural Network and its implementation for solution of ASD (autism spectrum disorder) classification.
  • research and development of physics-based algorithm and software: entropy methods in ASD feature discovery, and pattern classification.
  • INTELLECTUAL PROPERTY (IP) DISCLOSURE: Novel algorithms and methodology in medicine of ASD, disclosed to WARF for patent application.
Details:

This is a study on autism spectrum disorder (ASD). Our experiments use a collection of anonymized clinical time series gathered at Waisman Center of UW-Madison as part of an IRB-approved study. the goal here is to analyze and process massive raw data gathered at Motor Brain and Development Lab. from volunteers. Each data file corresponds to one human subject going through specifically designed procedures or poses. A row in each file records two types of sensory data at a specific time (Timestamp). The first type contains balance board data which records the Subject’s center of gravity with respect to the center of the board. The second type of sensory data is Kinect camera data of subject’s position. This data is generated by processing Kinect’s generated video to indicate specific points on subject's body and track them. Overall the image processing method tracks the cartesian coordinates of 20 points on the subject’s body in XYZ coordinates.

As a data analyst, our job was to first clean the dataset from various noises usually associated with this kind of data. At this point, we have proposed two methods to study this data: First methods is based on physical aspects of the problem and focuses Entropy as a main feature of the motion data. The second method is based on our specialized Deep recurrent Neural Network architecture that builds on a vast amount of work in this context.

Under Supervission of Prof. B. Gerhart

Dec 2016-Aug 2017


Keywords:
Finantial Data Analisys Compenstaion Human Resource Data Analitics Bigdata DataScience

Highlights:
  • FINANCIAL DATA ANALYTICS: Implement interactive application to manage and Analyse the Financial dataset
  • Case In Compensation: implement an integrated case on pay model and Compensation used in the HR Compensation textbook.
Details:

Cases in Compensation contains an integrated case, with three phases that parallel the pay model used in the Compensation textbook. The case is designed to provide students, generally working in teams, the opportunity to address the major decisions in designing a compensation system, thus applying the theories and concepts in the textbook.

As a data analyst, our job was to redesign and improve the case. During this job, we managed and processed the financial proprietary dataset on compensation and pay plans. The result of this work is the CasesInCompensation application which accompanies the case study on the subject that helps HR (Human resource) student to role play as compensation specialist in a small software company.

Under Supervission of Prof. B. Alizadeh

Jan 2014-jun 2015


Keywords:
Stochastic methods Monte-Carlo Tree Search CAD Development Graph Learning GAUT HLS Design Compiler

Highlights:
  • Work as research assistant on power-aware High level synthesis tools and high-performance low-cost machine-learning solutions
  • Design and Implementation of a DSP-specific, low-power HLS tool
  • Research on a Monte-Carlo Tree Search(MCTS) Based Scheduling algoritm

Publications:
  1. Ehsan Qasemi, Mohammad H. Shadmehr, Bardia Azizian, Amir Samadi, Sajjad Mozaffari,Amir Shirian and Bijan Alizadeh, “Highly Scalable, Shared Memory , Monte-Carlo Tree Search based Blokus Duo Solver on FPGA ”, International Conference on Field-Programmable Technology (FPT), 2014.

Details:

One main challenge in High-Level Synthesis (HLS) field is the exponential run-time order of its scheduling phase. in this phase, the goal is to reach optimum scheduling of atomic operations in reasonable time.
Until now many algorithms have been introduced to obtain optimal and suboptimal scheduling, but they are mainly based on heuristic method. For instance, Force-Directed List Scheduling (FDLS), has been introduced which is one of the most efficient heuristic scheduling algorithms. This algorithm gives an optimal scheduling result from the perspective of generated hardware's latency. However, the main problem is the fact that the weight calculations required in this algorithm, have a huge computation load which makes FDLS useless for larger circuits.
To alleviate this problem, we inspire the works performed in the field of Artificial Intelligence (AI) gaming decision makings in such a way that we migrate from heuristic methods to stochastic and random simulation based methods. In such methods, instead of making a decision with weight assignment, random simulation is used. During random simulation process, suitable random decisions are made until no decision is possible to be made. At the end of the random simulation process, we can indicate whether the random decision results in success or failure. Based on such information, a global knowledge decision tree is obtained which results in more efficient as well as faster decisions to be made in comparison with heuristic methods.
Our AI-based scheduling as well as, other available scheduling algorithms have been implemented as an HLS tool in C++. The implemented scheduling algorithms include FDLS, List, FAMOS, Genetic Algorithm, etc. Our HLS tool gets CDFG generated from GAUT's output as input graph, performs scheduling, binding, and synthesizes the design in SystemVerilog language. Implemented HLS tool also considers the real synthesis results such as latency and power consumption, from design compiler for each atomic operation to get practical results.

Under Supervission of Prof. B. Alizadeh

Jun 2014-Aug 2015


Keywords:
Monte-Carlo Tree Search Shared Memory Architecture Massively Parallel Architecture AI Agent

Highlights:
  • HW/SW co-design of Highly parallel Blokus-Duo Solver based on Monte Carlo Tree Search (MCTS) Engine on Terasic DE2-115 FPGA board

Publications:
  1. Ehsan Qasemi, Mohammad H. Shadmehr, Bardia Azizian, Amir Samadi, Sajjad Mozaffari,Amir Shirian and Bijan Alizadeh, “Highly Scalable, Shared Memory , Monte-Carlo Tree Search based Blokus Duo Solver on FPGA ”, International Conference on Field-Programmable Technology (FPT), 2014.

Details:

A group of 9 undergraduate students from ECE of UT has been organized by Prof. Bijan Alizadeh. I have been given the supervision task to first train these students on MCTS and hardware design, and second manage them to implement an MCTS based Blokus-duo engine on FPGA to participate in the ICFPT2014 design competition which was held on Dec 2014 in China.

This work has been in Silicone Intelligence (SI) Lab under supervision of Prof. Sied Mehdi Fakhrae as my internship

Jul 2013-Apr 2014


Keywords:
SRAM Memory Sub-Threshold Design Low-Power Circuits

Highlights:
  • Work as research assistant on low power SRAM memory cells to operate in subthreshold voltages.
  • Design an electronic design automation procedure to obtain custom designs in layout using SKILL scripting language.
  • Design & Implementation of an Automatic SRAM Memory Generator CAD tool with capability of designing Low-power SRAMs with configurable cells working in both Sub-threshold and super-threshold regions in 180nm technology.

Publications:
  1. Ghasem Pasandi, Sied Mehdi Fakhraie, and Ehsan Qasemi, "A New Tri-State Based Static Random Access Memory (SRAM) Cell with Improved Write Ability and Read Stability," accepted for publication in CSI Journal on Computer Science and Engineering, April 2014.
  2. Ghasem Pasandi, Ehsan Qasemi, and Sied Mehdi Fakhraie, "A New Low Leakage TGate Based 8T SRAM Cell with Improved Write-Ability in 90nm CMOS Technology," in 22nd Iranian Conference on Electrical Engineering(ICEE), Tehran, Iran. May 2014.

Details:

SRAMs are the most popular embedded-memory option for CMOS IC design. They are widely used for high-speed read and write operations, but due to their large area and high power consumption, absorb a large percentage of total power and area of chips. Therefore, efforts made on designing optimum cells to reduce whole SRAM blocks power consumption leads to major savings in total power of the single chip. Conventional 6T SRAM cell has good area density, performance, and reliability in 90nm, 65nm, and 45nm technologies; but these facts are only obtained for supply voltages above 0.8V where circuits operate at the super-threshold region. As supply voltage drops, sensitivity to all sorts of variations is increased, so the true functionality of SRAMs is spoiled. So in order to have practical sub-threshold SRAM memories new cell designs are required.
In this project we introduced two SRAM cell architectures, both work in the sub-threshold region. out first cell is based on T-Gate. in this architecture we added a T-Gate in back-to-back inverters feed back to cut the feedback during write operation which increases the SRAM write noise margin and guaranties the successful write. In our second architecture we used the Tri-state concept in digital design. in this architecture, we added a group of shared pass transistors to cell's supply lines and by cutting off this supply lines during write operation we increased the Write Noise Margin (WNM) as well as Hold Noise Margin (HNM).
In order to proof the functionality of our design in real world we designed a CAD tool to generate a configurable SRAM memory in tsmc180 nm technology. In our tool the cell architecture and size of memory are configurable and a user can generate the memory with desired parameters. The tool gets a layout of the desired cell as well as some specifications like number of supply lines, their geometry in layout, number of control signals, and analog features of the cell; finally, the tool generates the specified memory in both Transistor and layout level. the tool is implemented in both MATLAB and SKILL languages and layouts are generated using Cadence:Virtuoso tool

This work have been performed in TLM Lab under supervision of Prof. Zain Navabi. This design was announced as the "Best Design" in "Iran's 1'st National Digital System Contest (FPGASoc 2013)" in fall 2013.

Nov 2013-Dec 2013


Keywords:
Encription/Decryption AES High Performance Computing

Highlights:
  • HW/SW co-design of AES encryption/decryption algorithm on FPGA platform (Terasic DE2-115 FPGA board) (FPGASoC Design Competition).

Publications:
  1. M. Biglari, E. Qasemi, B. PourMohseni, “Maestro: A High-Performance AES Encryption/Decryption System”, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013), October 30-31, 2013, School of Computer Science, IPM, Tehran, Iran.

Details:

High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost-efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high-performance AES encryption/decryption. A ten-stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in the design of AES engine which enables it to reach a throughput of 12.8 Gbps. First, tightly coupled encryption and round key generation units in encryption unit, and second, ahead of time round key generation in decryption unit. Altera DE2-115 development and educational FPGA board is used as the platform for Maestro. In the proposed architecture the DMA modules act as interfaces between data sources and data sinks by loading the input data into AES engine and taking encrypted and generated test data to target memories.

This work have been performed in TLM Lab under supervision of Prof. Zain Navabi.

Nov 2013-Dec 2013


Keywords:
Assertion Based Verification Formal Methods Utopia ATM Switch

Highlights:
  • Research on formal verification methods using temporal logic
  • Hardware implementation of a synthesizable Utopia ATM communication module in System Verilog on Terasic DE2 FPGA board
  • Implementing an Object-Oriented based random constrained test bench as Verification method

Details:

Assertion Based Verification(ABV) is one the most applicable verification methods in today's industry. In case of ABV the SystemVerilog(SV) the most useful hardware description language. SV is an HDL and HVL language containing both low-level constructs of Verilog and system-level components and data types of C language combined with Object-Oriented features of C++. This language creates the opportunity of combining the hardware description language with advanced features of OO programming to create a powerful platform for design and verification of HW/SW systems on a single platform. In this work, we implemented the Utopia ATM communication module with synthesizable SV and design an OO testbench based on random constraint testbench method.

R&D Experience

MAY 2016-AUGUST 2016



Highlights:
  • Generate the Costume Linux based OS for Atmel sam9 and Qualcomm Atheros micro-controllers
  • Patch and Cross Compile the python 2.7.3 source code for Atmel sam9
  • Write a python based web server to manage a cryptographic network node to secure the communication
  • write a low-level C application as the backbone of the server to get maximum Enc/Dec performance

AUGUST 2014-JULY 2015


Highlights:
  • Design, implement and test an FPGA-based Hardware Security Module (HSM) to provide a secure platform for bank applications such as money transactions, on Zync7100 SoC platform.
  • Manage the HW team to Design the FPGA-based hardware to implement wide range of cryptography algorithms in Chisel HDL (RSA, AES, 3DES, ECC, etc.)
  • Design the FPGA-based interfaces and HW wrappers to communicate to Linux-based custom OS in Chisel HDL
  • Design and Implement the HW verification procedure to perform the NIST test on HW in an automated environment in Java, Scala, and Chisel HDL
  • Implement the low-level OS kernel functions to communicate with the AXI-STREAM and AXI-FULL interfaces to gain maximum performance in C

JUNE 2013-JANUARY 2014


Highlights:
  • Worked effectively with design and test teams to design embedded and low-cost solutions to improve performance and precision
  • Create a set of micro-controller based embedded solutions to manage simple tasks in the product
  • Design and implement a low-cost Genetic algorithm (GA) based controller hardware to operate a mechanical arm on FPGA platform
  • Design set of procedures to automate the test and verification steps of the product

Teaching Experience

  • ECE 552: Introduction to Computer Architecture (Prof. Yu H. Hu) Fall 2016

  • ECE 352: Digital System Fundamentals (K. Morrow, X. Zhang) Spring 2016

  • ECE 252: Introduction to Computer Engineering (K. Morrow, M. Morrow) Spring 2016

  • LCA 601,563: Advanced Persian Language (E. Barnard) Fall 2016

  • LCA 602,564: Advanced Persian Language (E. Barnard) Spring 2017

  • ECE 615: Electronic System Level Design (B. Alizadeh) Spring 2015

  • ICEEP: Embedded Linux Workshop (Z. Navabi) Summer 2014

  • ECE 367: Digital Logic Design lab (Z. Navabi) Spring 2013,2014, Fall 2013, Summer 2014

  • ECE 532: Object-Oriented Simulation of Electronic Systems (Z. Navabi) Spring 2013, 2014

  • ECE 642: FPGA Base Embedded System Design (B. Alizadeh) Fall 2013, 2014

  • ECE 423: Computer Architecture (S. Safari) Spring 2014

  • Introduction to Computer and Computing Systems (H. Moradi) Fall 2012

Notable Academic Projects

  • Matrix Completion with SDP to reduce noise and jitter in human motion data

  • Monte-Carlo Tree Search Algorithms for Parallel Platforms in CUDA, OpenMP, and MPI

  • Neural Network based Sonar Radar in Python

  • Hand writing recognition with Neural networks in Python

  • Real-time, RLS based, Adaptive noise cancellation FIR filter on DSK6700, DSP boards

  • Harmonic Synthesizer with Gender Identification Based on AC Pitch Estimation Method

  • Skin Detection Algorithm for NVIDIA GPU platforms in CUDA

  • Automated adaptive voice recorder tool based on PESQ speech quality evaluation method

  • Study on parallel sorting methods (RADIX, Bubble, Merge, and Quick) in MPI

  • Study on Data predictions (TAGE and V-TAGE) in Modern Processor Architecture

  • ARM based pipeline Process with Data prediction and 2-way set associative Cache

  • Low-level OS exploits using Aleph One’s code (Stack Smashing, Double free, Format String)

  • Study on Split Manufacturing method in Chip manufacturing and it's explitation methods

Voluntary & Leadership Experience

  • President of Persian Student’s Society of UW Madison (PSS), 2015-2017

  • Board member of First Iranian FIlm Festival at Madison, WI, Spring 2017

  • Organize and Lead group of undergrad students to participate in:
    ICFPT Design Competition, Summer and Fall 2014-15
    FPGASoC Design competition, Winter 2014

  • World-Wide Culture day at Madison’s East High School, Fall 2016