This research focuses on our proposed hardwarearchitecture on a highly scalable, shared-memory, MonteCarlo Tree Search (MCTS) based Blokus-Duo solver. In theproposed architecture each MCTS solver module contains acentralized MCTS controller which can also be implementedusing soft-cores with a true dual-port access to a sharedmemory called main memory, and multitude number of MCTSengines each containing several simulation cores.Consequently, this highly flexible architecture guaranties theoptimized performance of the solver regardless of the actualFPGA platform used. Our design has been inspired fromparallel MCTS algorithms and is potentially capable ofobtaining maximum possible parallelism from MCTSalgorithm. On the other hand, in our design we combineMCTS with pruning heuristics to increase both the memoryand LE utilizations. The results show that our architecture canrun up to 50MHz on DE2-115 platform, where eachSimulation core requires 11K LEs and MCTS controllerrequires 10K LEs.
For implementation, I supervised a group of 9 undergraduate students from ECE of UT through their training (both in algorithm and hardware design) for 1 month and finally through their hardware implementation of the MCTS based Blokus-duo engine on FPGA to participate in the ICFPT2014 design competition which was held on Dec 2014 in China.