• -> Study on power-aware High level synthesis tools and high-performance low-cost machine-learning solutions
• -> Design and Implementation of a DSP-specific, low-power HLS tool
• -> Research on a Monte-Carlo Tree Search(MCTS) Based Scheduling algorithm

1. Qasemi E, Samadi A, Shadmehr MH, Azizian B, Mozaffari S, Shirian A, Alizadeh B. Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. In2014 International Conference on Field-Programmable Technology (FPT) 2014 Dec 10 (pp. 370-373). IEEE.

we address the problem ofscheduling during high-level synthesis (HLS). Instead of usingor improving existing heuristics like Force Directed ListScheduling (FDLS), we propose a new scheduling algorithmwhich is based on Monte-Carlo (MC) simulation. In theproposed scheduling algorithm, MC Tree Search (MCTS)method as the heart of our scheme handles the schedulingproblem with both timing and resource constraints. The resultsshow that our method is able to schedule large industrial testcases up to two orders of magnitude faster than existingmethods such as FDLS with up to 15% better latency.