Subthreshold Memory Compiler
Highlights:
  • -> Design memory compiler tool for assembling SRAM memory cells into full size memories
  • -> Proposed T-Gate based SRAM cell design that improves write-ability of conventional designs in subthreshold operating region
  • -> Propose a 8-Transistor SRAM cell that improves Write Noise Margin (WNM) by 60% over conventional 6T cel
Publications:
  1. Pasandi G, Qasemi E, Fakhraie SM. A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology. In2014 22nd Iranian Conference on Electrical Engineering (ICEE) 2014 May 20 (pp. 382-386). IEEE.
  2. Pasandi G, Fakhraie SM, Qasemi E. A New Tri-State Based Static Random Access Memory (SRAM) with Improved Write-Ability and Read Stability. In2014 JCSE Vol. 10, No.2 & 4, Summer 2012 & Winter 2013

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